The integrated circuit (IC) manufacturing technology have been moving forward as the metal-oxide-semiconductor field-effect transistors (MOSFETs) become smaller and smaller to improve the performances such as increased switching speed, lowered power consumption and higher level of integration. HKMG (high-k metal gate) technology promises to enable scaling of the transistors as well as reduced stand-by power due to a reduction in gate leakage.
In the HKMG technology, an interlayer dielectric layer is typically polished by a chemical-mechanical polishing (CMP) process before removing a polysilicon dummy gate. The CMP process of the interlayer dielectric layer is important for the performance of the metal gate formed in subsequent steps. After polishing, however, seams, voids or scratches may form on the surface of the interlayer dielectric layer, and metal residues may remain therein after deposition and polishing of a metal layer for forming a metal gate. As a result, electrical shorts or metal bridging may occur.
To overcome these problems, U.S. Pat. No. 7,799,630, for example, discloses a method for forming a metal gate using CMP and etching back processes. However, the seams, voids or scratches still exist.
Accordingly, there is need in providing a method for planarizing a semiconductor device that is free of seams, voids or scratches on the surface of the interlayer dielectric layer.